1. Field of the Invention
This invention relates to graphics memories, and more particularly to video memories with block-write operations using a wide interface.
2. Description of the Related Art
Graphics systems use graphics or video memory to store display information. The display information is commonly stored as a bit-map of the lines of pixels displayed on a display screen, or as textual characters which index a character bit-map to convert the characters to pixels. The video memory stores all of the pixels in display frame, and these pixels are sequentially fetched to refresh a display screen, such as a cathode-ray-tube (CRT) or a flat-panel display.
The host processor, which executes user programs and the operating system, updates the displayed image by writing new pixels to the video memory. Many parts of the screen display the same color without any foreground features. For example, a window may have a large amount of white space, while a desktop background may be a featureless blue color. Moving the window causes the host processor to update the bit-map of the screen in the video memory by writing new pixels to the video memory. Since large parts of the screen are of the same color, many of the pixels written to the video memory are identical. The data values written from the host processor to the video memory are likewise identical for these identical pixels.
Specialized memory chips are available which exploit the fact that many identical pixels are written to the video memory during host updates. A block-write mode allows the data or pixel to be written once to the memory chip, and then copied by the chip to multiple locations in the memory. Thus the host processor does not have to write each pixel location on the screen, but can write larger blocks of identical pixels at the same time using a block write operation.
8-BIT BLOCK-WRITE--FIG. 1
FIG. 1 is a diagram of a prior-art graphics memory with an 8-bit block-write register. An example of such a graphics memory chip with a block-write mode is disclosed in U.S. Pat. No. 5,319,606 to Bowen et al. for "Blocked Flash Write in Dynamic RAM Devices" assigned to IBM Corp. of Armonk, N.Y. An 8-bit data bus (DQ) 20 receives an 8-bit data value representing a pixel from the host processor. Special mode pins on the chip are activated so that the data from data bus 20 is written to color register 16 rather than to RAM array 10. Mask register 14 may likewise be written by the host using data bus 20. A mask written into mask register 14 is used by mask logic 18 to prevent some of the bits from being written. For example, setting the mask bits 6, 7 in mask register 14 prevents bits 6 and 7 of the pixel data in color register 16 from being written to RAM array 10. Masking is useful when only a portion of the pixel is changed, and at the edges of a block being written.
The un-masked bits of pixel data from color register 16 are then written to multiple locations in RAM array 10 when a block-write pin on the chip is activated, or some other sequence or combination of signals is asserted. Column drivers 12 replicate the pixel data from color register 16 to eight columns of 8-bits each in RAM array 10. While all 8 columns could be written at one time, some of the columns may be disabled by driving a zero onto the corresponding bit of data bus 20. Driving a one onto a data bit of data bus 20 enables writing to a column. Thus data bus 20 acts as a column select or enable bus during block write, enabling or disabling some of the columns of column drivers 12. The bit masked is specified on data bus 20 at the trailing edge of the row-address strobe (RAS) when write-enable (WE) is active. Mask logic 18 may also be integrated with column drivers 12 to disable driving masked bits.
A block write can write up to 8 columns of 8-bits per column, a total of 64 bits. For a typical pixel, 16 bits are used for each pixel, although older 8-bit pixels are still used for some graphics resolutions. Thus the 64 bits written during a block write are only 64/16=4 pixels. Since color register 16 is only 8 bits wide, each block of 16-bit pixels require two loads of color register 16 and two block writes.
FOUR STEPS TO BLOCK-WRITE PIXELS WITH 8-BIT COLOR REGISTER
FIG. 2 highlights that at least four steps are needed to block-write 16-bit pixels using an 8-bit color register. A 16-bit pixel has a first 8-bit half X1 and a second 8-bit half X2, so that the whole 16-bit pixel is represented by X1:X2. The first step is to write the first half of the pixel, X1, to the 8-bit color register 16 of FIG. 1. A block write is performed in the second step, where X1 from the color register is written to 3 of the 8 columns by setting data bus 20 to 10101000. Five of the columns are not written. The last two columns are not written because a foreground image has already been written to the pixel in the last two column. The background color fill only writes the three pixels in columns 1-6.
Since only 8 bits of the 16-bit pixel may be loaded into the 8-bit color register, the second half of the pixel, X2, is written to the color register in step 3. Then in step 4 the second half of the pixel is block-written to columns 2, 4, 6 by setting data bus 20 to 01010100. This 4-step procedure wrote 3 full pixels using block-write, which is more efficient than the 6 steps requires to randomly write the 3 16-bit pixels using an 8-bit data bus. When the mask register is also used, then an additional step is needed to load the mask register.
FIG. 3 highlights that each block-write operation in general requires three steps: one step to load the pixel data into the color register, a second step to load the mask value into the mask register, and a third step to write the pixel data to multiple columns in RAM array 10. In step 1, the pixel data is written to color register 16 over data bus 20. In step 2, the mask value is written to mask register 14 over data bus 20. In step 3, the pixel data from color register 16 is optionally masked by mask logic 18, and then input to column drivers 12. Column-enable signals are input on data bus 20 to enable some or all of the 8 columns by enabling column drivers 12.
FIG. 4 is a timing diagram illustrating the three steps required to use block write in the graphics memory chip of FIG. 1. In step 1, during time period 22, data bus 20 (DQ) transmits the pixel or color data to the color register where it is stored for a subsequent block-write. RAM array 10 is idle since the data is written to the color register external to the RAM array. In step 2, during time period 23, data bus 20 (DQ) transmits the mask value to the mask register where it is stored for a subsequent block-write. RAM array 10 is again idle since the data is written to the mask register external to the RAM array. In step 3, during time period 24, the pixel data from the color register is masked and replicated by the column drivers and written to multiple locations in the RAM array, which is active. The data bus is used for the column-enable signals rather than for data. When the same pixel is written to many locations, the first step can be skipped for later block writes using the same pixel data, improving efficiency somewhat.
32-BIT COLOR REGISTER--FIG. 5
The limited size of the block write of FIGS. 1-2 can be improved by a wider color register. The MT41LC256K32D4 synchronous graphics RAM (SGRAM) chip by Micron Technology of Boise, Id. is an example of a 32-bit graphics memory chip. FIG. 5 is a diagram of a graphics memory chip with a 32-bit color register. Data bus 20' is 32-bits wide, and writes a 32-bit mask to mask register 14' or 32 bits of pixels data to color register 16'. During the second step, when the pixel data from color register 16' is written to RAM array 10', the 32 data bus 20' lines act as 32 byte-enables for the eight 4-byte columns driven by column drivers 12'. Four byte-enables 21 (DQM) are also provided to disable bytes during normal writes.
The 32-bit color register can hold two 16-bit pixels, and a block-write operation writes up to eight 32-bit columns, or 256 bits. This is equivalent to 16 pixels in a single block-write operation. However, the wider interface requires more pins on the chip and a more expensive package than the 8-bit color register.
FIG. 6 illustrates block write using a 32-bit color and mask registers. The 32-bit color register holds two complete 16-bit pixels, X, Y, while the 32-bit mask register contains a 32-bit mask value. In step 1, pixels X and Y are loaded into the color register. During step 2, the mask value is written to the mask register. In step 3, these pixels are masked and written to multiple locations in the RAM array as a block write. FIG. 6 shows that one pixel 26 is disabled by de-asserting the corresponding column/byte select signal on data bus 20'.
The 32-bit color register can hold two different pixels. While both pixels can be the same color when a solid color fill is desired, more complex backgrounds are common today. These complex backgrounds use multiple colors or shades of color to display a complex background pattern, such as a multi-colored wallpaper on a Windows-based PC. Simply extending the size of the color register to accommodate more pixels is problematic since the data bus also increases in size, and the number of pins on a memory chip is limited. It is therefore desired to perform complex pattern fills rather than simple one- or two-color fills. It is desired to integrate the graphics memory onto the same die as the graphics controller to reduce the number of pins required.
While block-write functions are useful, a more efficient block-write operation is desired. It is desired to perform block write in a single step without first loading a color or a mask register.